In the latter half of the twentieth century, there began a phenomenon known as the information revolution. While the information revolution is a historical development broader in scope than any one event or machine, no single device has come to represent the information revolution more than the digital electronic computer. The development of computer systems has surely been a revolution. Each year, computer systems grow faster, store more data, and provide more applications to their users.
A modern computer system typically comprises one or more central processing units (CPU) and supporting hardware necessary to store, retrieve and transfer information, such as communication buses and memory. It also includes hardware necessary to communicate with the outside world, such as input/output controllers or storage controllers, and devices attached thereto such as keyboards, monitors, tape drives, disk drives, communication links coupled to a network, etc. CPU's (also called processors) are capable of performing a limited set of very simple operations, but each operation is performed very quickly. Data is moved between processors and memory, and between input/output devices and processors or memory. Sophisticated software at multiple levels directs a computer to perform massive numbers of these simple operations, enabling the computer to perform complex tasks, and providing the illusion at a higher level that the computer is doing something sophisticated.
Continuing improvements to computer systems can take many forms, but the essential ingredient of progress in the data processing arts is increased throughput, i.e., performing more of these simple operations per unit of time.
The computer is a sequential state machine in which signals propagate through state storing elements synchronized with one or more clocks. Conceptually, the simplest possible throughput improvement is to increase the speeds at which these clocks operate, causing all actions to be performed correspondingly faster.
Data must often be communicated across boundaries between different system components. For example, data may need to be communicated from one integrated circuit chip to another. In countless instances, an operation to be performed by a component can not be completed until data is received from some other component. The capacity to transfer data can therefore be a significant limitation on the overall throughput of the computer system. As the various components of a computer system have become faster and handle larger volumes of data, it has become necessary to correspondingly increase the data transferring capability (“bandwidth”) of the various communications paths.
Typically, a communications medium or “bus” for transferring data from one integrated circuit chip to another includes multiple parallel lines which carry data at a frequency corresponding to a bus clock signal, which may be generated by the transmitting chip, the receiving chip, or some third component. The multiple lines in parallel each carry a respective part of a logical data unit. For example, if eight lines carry data in parallel, a first line may carry a first bit of each successive 8-bit byte of data, a second line carry a second bit, and so forth. Thus, the signals from a single line in isolation are meaningless, and must somehow be combined with those of other lines to produce coherent data.
The increased clock frequencies of processors and other digital data components have induced designers to increase the speeds of bus clocks in order to prevent transmission buses from becoming a bottleneck to performance. This has caused various design changes to the buses themselves. For example, a high-speed bus is typically implemented as a point-to-point link containing multiple lines in parallel, each carrying data from a single transmitting chip to a single receiving chip, in order to support operation at higher bus clock speeds.
It is impossible to avoid certain variations among the lines of a single parallel link (whether a result of manufacturing tolerance, line geometry, or other factors. These variations become more critical as bus speeds are increased). In order to support inter-chip data transfer at high bus clock speeds, the lines of a data communications bus can be individually calibrated to compensate for these and other variations. However, so sensitive is the communications mechanism in many modern data processing environments that calibration parameters can drift significantly during operation, so that periodic re-calibration is required to achieve acceptable performance.
Calibration of the lines of a parallel link may require that multiple factors be taken into account and compensated for, such as variations in timing, voltage offsets, signal amplification, interference from adjacent data bits, and so forth. Support for calibration and periodic recalibration of the lines may require complex analog and other circuitry which can sense discrepancies and/or be tuned to accommodate them. Such complex circuitry can add significantly to the cost and power consumption of the chip.
Recently, there has been interest in an electronic packaging technique involving the mounting of multiple integrated circuit semiconductor chips on a single silicon carrier. Conceptually, this is similar to conventional techniques which mount multiple chips on a single printed circuit board having a fiberglass or other polymeric base and one ore more layers of circuit patterns embedded therein, the silicon carrier substituting for the conventional printed circuit board. However, the silicon carrier is substantially smaller than the conventional printed circuit board, and supports packaging of integrated circuits at significantly higher densities.
Another recent electronic packaging development involves 3D chip stacking, in which multiple integrated circuit semiconductor chips are stacked one on top of another, to connect directly with other chips in the stack without an intermediary carrier. This technique similarly supports packaging at significantly higher densities.
The use of the silicon carrier and/or 3D chip stacking introduces new engineering challenges. In particular, the increased circuit density aggravates the problems of heat generation and dissipation, and makes reduced power consumption a high priority.
Data communications buses for communicating data among multiple integrated circuit chips consume significant portion of the power consumed by the chips. Continuous calibration only increases the power requirements of these buses. A need exists for improved devices or methods which reduce power consumption in data communications buses, and in particular, in data communications buses which are continuously calibrated and/or may be used to communicate data among chips mounted on silicon carriers or chips directly connected with one another in a 3D stack arrangement.